EtherCAT FPGA IP Core Version Master
Developed a master stack IP core that operates solely in the FPGA logic area.
The "EtherCAT FPGA IP Core Version Master" is software that enables high-speed cyclic communication of less than 100μsec. It mainly includes master functions such as compliance with ETG.1500 class B, cable redundancy features, and DC functions. Please feel free to consult us if you have any requests. 【Features】 ■ Stable communication intervals with jitter around 25nsec ■ CPU area can be freely designed from the OS level ■ Can operate on the customer's design board with the provision of the IP core *For more details, please download the PDF or feel free to contact us.
- Company:ケイエスジェイ
- Price:Other